4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor - researchr publication authors

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Penny Li, Jinuk Luke Shin, Georgios Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister. 4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015. pages 1-3, IEEE, 2015. [doi]

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