A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement - researchr publication related

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Qi Li, Bo Wang, Tony T. Kim. A 5.61 pJ, 16 kb 9T SRAM with single-ended equalized bitlines and fast local write-back for cell stability improvement. In Proceedings of the 2012 European Solid-State Device Research Conference, ESSDERC 2012, Bordeaux, France, September 17-21, 2012. pages 201-204, IEEE, 2012. [doi]

The following publications are possibly variants of this publication:

Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency ImprovementBo Wang, Truc Quynh Nguyen, Anh-Tuan Do, Jun Zhou, Minkyu Je, Tony Tae-Hyoung Kim. tcas, 62-I(2):441-448, 2015. [doi]

Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMsBo Wang, Qi Li, Tony Tae-Hyoung Kim. tvlsi, 24(6):2165-2173, 2016. [doi]

Access Characteristic Guided Read and Write Cost Regulation for Performance Improvement on Flash MemoryQiao Li, Liang Shi, Chun Jason Xue, Kaijie Wu, Cheng Ji, Qingfeng Zhuge, Edwin Hsing-Mean Sha. FAST 2016: 125-132 [doi]

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage ComputingTony Tae-Hyoung Kim, Jason Liu, John Keane 0001, Chris H. Kim. jssc, 43(2):518-529, 2008. [doi]

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