A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM - researchr publication authors

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Yixi Li, Zhao Zhang 0004, Yong Chen 0005, Xinyu Shen, Zhao Zhang, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu. A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2023, Haikou, China, November 5-8, 2023. pages 1-3, IEEE, 2023. [doi]

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