The following publications are possibly variants of this publication:
- A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue AmplifierXinsheng Wang, Maosong Shi, Peizhe Li, Jianwei Liu, Zhangcheng Huang, Chixiao Chen, Wenning Jiang. iscas 2023: 1-5 [doi]
- A 0.45mW 12b 12.5MS/s SAR ADC with digital calibrationWei Li, Tao Wang, Jorge A. Grilo, Gabor C. Temes. cicc 2014: 1-4 [doi]
- A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time GenerationMeng Ni, Xiao Wang 0021, Fule Li, Zhihua Wang 0001. tvlsi, 29(7):1416-1427, 2021. [doi]
- A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification StageYi Shen 0007, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, Ruixue Ding, Zhangming Zhu. cicc 2023: 1-2 [doi]