Ran Li, Qi Zhao, Ting Yi, Zhiliang Hong. A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOS. In 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011. pages 500-503, IEEE, 2011. [doi]
@inproceedings{LiZYH11,
title = {A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOS},
author = {Ran Li and Qi Zhao and Ting Yi and Zhiliang Hong},
year = {2011},
doi = {10.1109/ASICON.2011.6157231},
url = {http://dx.doi.org/10.1109/ASICON.2011.6157231},
researchr = {https://researchr.org/publication/LiZYH11},
cites = {0},
citedby = {0},
pages = {500-503},
booktitle = {2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011},
publisher = {IEEE},
isbn = {978-1-61284-192-2},
}