Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Seian-Feng Liao, Kai-Neng Tang, Ming-Dou Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin. Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. In European Conference on Circuit Theory and Design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015. pages 1-4, IEEE, 2015. [doi]

This author has not been identified. Look up 'Seian-Feng Liao' in GoogleThis author has not been identified. Look up 'Kai-Neng Tang' in GoogleThis author has not been identified. Look up 'Ming-Dou Ker' in GoogleThis author has not been identified. Look up 'Jia-Rong Yeh' in GoogleThis author has not been identified. Look up 'Hwa-Chyi Chiou' in GoogleThis author has not been identified. Look up 'Yeh-Jen Huang' in GoogleThis author has not been identified. Look up 'Chun-Chien Tsai' in GoogleThis author has not been identified. Look up 'Yeh-Ning Jou' in GoogleThis author has not been identified. Look up 'Geeng-Lih Lin' in Google

runs on WebDSL