Seian-Feng Liao, Kai-Neng Tang, Ming-Dou Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin. Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. In European Conference on Circuit Theory and Design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015. pages 1-4, IEEE, 2015. [doi]
Abstract is missing.