Seian-Feng Liao, Kai-Neng Tang, Ming-Dou Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin. Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. In European Conference on Circuit Theory and Design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015. pages 1-4, IEEE, 2015. [doi]
@inproceedings{LiaoTKYCHTJL15,
title = {Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection},
author = {Seian-Feng Liao and Kai-Neng Tang and Ming-Dou Ker and Jia-Rong Yeh and Hwa-Chyi Chiou and Yeh-Jen Huang and Chun-Chien Tsai and Yeh-Ning Jou and Geeng-Lih Lin},
year = {2015},
doi = {10.1109/ECCTD.2015.7300108},
url = {http://dx.doi.org/10.1109/ECCTD.2015.7300108},
researchr = {https://researchr.org/publication/LiaoTKYCHTJL15},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {European Conference on Circuit Theory and Design, ECCTD 2015, Trondheim, Norway, August 24-26, 2015},
publisher = {IEEE},
isbn = {978-1-4799-9877-7},
}