A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers

Yong Lim, Michael P. Flynn. A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers. J. Solid-State Circuits, 50(10):2331-2341, 2015. [doi]

Authors

Yong Lim

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Michael P. Flynn

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