Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design

Rong Lin. Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design. In 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA. pages 325-330, IEEE Computer Society, 2001. [doi]

Authors

Rong Lin

This author has not been identified. Look up 'Rong Lin' in Google