Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding

Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu. Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding. IEEE Trans. VLSI Syst., 19(2):305-318, 2011. [doi]

Authors

Cheng-Hung Lin

This author has not been identified. Look up 'Cheng-Hung Lin' in Google

Chun-Yu Chen

This author has not been identified. Look up 'Chun-Yu Chen' in Google

An-Yeu Wu

This author has not been identified. Look up 'An-Yeu Wu' in Google