Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization

Mark Po-Hung Lin, Chih-Cheng Hsu, Yu-chuan Chen. Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems, 34(2):280-292, 2015. [doi]

Abstract

Abstract is missing.