The following publications are possibly variants of this publication:
- Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic MinimizationMark Po-Hung Lin, Yi-Ting He, Vincent Wei-Hao Hsiao, Rong-Guey Chang, Shuenn-Yuh Lee. tcad, 32(7):991-1002, 2013. [doi]
- Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DACMark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin. dac 2014: 1-6 [doi]
- Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuitsChien-Chih Huang, Chin-Long Wey, Jwu-E Chen, Pei-Wen Luo. todaes, 19(1):7, 2013. [doi]
- Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy CapacitorsCheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang. tcad, 31(12):1789-1802, 2012. [doi]
- Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio MatchingPo-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho. todaes, 21(3):39, 2016. [doi]
- PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor ArraysChien-Chih Huang, Jwu-E Chen, Chin-Long Wey. tcad, 36(1):134-145, 2017. [doi]