Low power 10-transistor full adder design based on degenerate pass transistor logic - researchr publication authors

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Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu. Low power 10-transistor full adder design based on degenerate pass transistor logic. In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012. pages 496-499, IEEE, 2012. [doi]

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