Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu. Low power 10-transistor full adder design based on degenerate pass transistor logic. In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012. pages 496-499, IEEE, 2012. [doi]
@inproceedings{LinHS12,
title = {Low power 10-transistor full adder design based on degenerate pass transistor logic},
author = {Jin-Fa Lin and Yin-Tsung Hwang and Ming-Hwa Sheu},
year = {2012},
doi = {10.1109/ISCAS.2012.6272074},
url = {http://dx.doi.org/10.1109/ISCAS.2012.6272074},
researchr = {https://researchr.org/publication/LinHS12},
cites = {0},
citedby = {0},
pages = {496-499},
booktitle = {2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012},
publisher = {IEEE},
isbn = {978-1-4673-0218-0},
}