Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

T. W. Lin, S. H. Ku, C. H. Cheng, C. W. Lee, Ijen Huang, Wen-Jer Tsai, T. C. Lu, W. P. Lu, K.-C. Chen, Tahui Wang, Chih-Yuan Lu. Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. In IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018. pages 6-1, IEEE, 2018. [doi]

This author has not been identified. Look up 'T. W. Lin' in GoogleThis author has not been identified. Look up 'S. H. Ku' in GoogleThis author has not been identified. Look up 'C. H. Cheng' in GoogleThis author has not been identified. Look up 'C. W. Lee' in GoogleThis author has not been identified. Look up 'Ijen Huang' in GoogleThis author has not been identified. Look up 'Wen-Jer Tsai' in GoogleThis author has not been identified. Look up 'T. C. Lu' in GoogleThis author has not been identified. Look up 'W. P. Lu' in GoogleThis author has not been identified. Look up 'K.-C. Chen' in GoogleThis author has not been identified. Look up 'Tahui Wang' in GoogleThis author has not been identified. Look up 'Chih-Yuan Lu' in Google

runs on WebDSL