T. W. Lin, S. H. Ku, C. H. Cheng, C. W. Lee, Ijen Huang, Wen-Jer Tsai, T. C. Lu, W. P. Lu, K.-C. Chen, Tahui Wang, Chih-Yuan Lu. Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. In IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018. pages 6-1, IEEE, 2018. [doi]
Abstract is missing.