Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability

Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi. Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. Integration, 43(2):176-187, 2010. [doi]

@article{LinKL10-0,
  title = {Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability},
  author = {Sheng Lin and Yong-Bin Kim and Fabrizio Lombardi},
  year = {2010},
  doi = {10.1016/j.vlsi.2010.01.003},
  url = {http://dx.doi.org/10.1016/j.vlsi.2010.01.003},
  tags = {analysis, design},
  researchr = {https://researchr.org/publication/LinKL10-0},
  cites = {0},
  citedby = {0},
  journal = {Integration},
  volume = {43},
  number = {2},
  pages = {176-187},
}