A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL - researchr publication

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You-Sheng Lin, Miao-Shan Li, Ching-Yuan Yang. A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL. In Proceedings of the ACM Symposium on Cloud Computing, SoCC 2019, Santa Cruz, CA, USA, November 20-23, 2019. pages 284-288, ACM, 2019. [doi]

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