Xiaohui Lin, Mohamed Megahed, Tejasvi Anand. A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail. In IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022. pages 188-189, IEEE, 2022. [doi]
@inproceedings{LinMA22,
title = {A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail},
author = {Xiaohui Lin and Mohamed Megahed and Tejasvi Anand},
year = {2022},
doi = {10.1109/VLSITechnologyandCir46769.2022.9830355},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830355},
researchr = {https://researchr.org/publication/LinMA22},
cites = {0},
citedby = {0},
pages = {188-189},
booktitle = {IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
publisher = {IEEE},
isbn = {978-1-6654-9772-5},
}