Transaction Level Error Susceptibility Model for Bus Based SoC Architectures - researchr publication authors

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Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada. Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. In 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA. pages 775-780, IEEE Computer Society, 2006. [doi]

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