Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada. Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. In 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA. pages 775-780, IEEE Computer Society, 2006. [doi]
@inproceedings{LinSVD06,
title = {Transaction Level Error Susceptibility Model for Bus Based SoC Architectures},
author = {Ing-Chao Lin and Suresh Srinivasan and Narayanan Vijaykrishnan and Nagu R. Dhanwada},
year = {2006},
doi = {10.1109/ISQED.2006.138},
url = {http://doi.ieeecomputersociety.org/10.1109/ISQED.2006.138},
tags = {rule-based, architecture},
researchr = {https://researchr.org/publication/LinSVD06},
cites = {0},
citedby = {0},
pages = {775-780},
booktitle = {7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-2523-7},
}