Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen. Efficient VLSI Design of Modulo 2:::n:::-1 Adder Using Hybrid Carry Selection. In Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China. pages 142-145, IEEE, 2007. [doi]
@inproceedings{LinSWZC07,
title = {Efficient VLSI Design of Modulo 2:::n:::-1 Adder Using Hybrid Carry Selection},
author = {Su-Hon Lin and Ming-Hwa Sheu and Kuang-Hui Wang and Jun-Jie Zhu and Si-Ying Chen},
year = {2007},
doi = {10.1109/SIPS.2007.4387534},
url = {http://dx.doi.org/10.1109/SIPS.2007.4387534},
tags = {design},
researchr = {https://researchr.org/publication/LinSWZC07},
cites = {0},
citedby = {0},
pages = {142-145},
booktitle = {Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China},
publisher = {IEEE},
isbn = {1-4244-1222-6},
}