Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen. Efficient VLSI Design of Modulo 2:::n:::-1 Adder Using Hybrid Carry Selection. In Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China. pages 142-145, IEEE, 2007. [doi]
Abstract is missing.