Yudeng Lin, Jianshi Tang, Bin Gao 0006, Qi Qin, Qingtian Zhang, He Qian, Huaqiang Wu. A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator. IEEE Trans. Circuits Syst. II Express Briefs, 70(4):1366-1370, April 2023. [doi]
@article{LinTGQZQW23,
title = {A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator},
author = {Yudeng Lin and Jianshi Tang and Bin Gao 0006 and Qi Qin and Qingtian Zhang and He Qian and Huaqiang Wu},
year = {2023},
month = {April},
doi = {10.1109/TCSII.2022.3224470},
url = {https://doi.org/10.1109/TCSII.2022.3224470},
researchr = {https://researchr.org/publication/LinTGQZQW23},
cites = {0},
citedby = {0},
journal = {IEEE Trans. Circuits Syst. II Express Briefs},
volume = {70},
number = {4},
pages = {1366-1370},
}