A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator - researchr publication

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Yudeng Lin, Jianshi Tang, Bin Gao 0006, Qi Qin, Qingtian Zhang, He Qian, Huaqiang Wu. A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator. IEEE Trans. Circuits Syst. II Express Briefs, 70(4):1366-1370, April 2023. [doi]

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