Chun-Yu Lin, Tun-Ju Wang, Tzu-Hsuan Liu, Tsung-Hsien Lin. An ultra-low power 169-nA 32.768-kHz fractional-N PLL. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017. pages 45-48, IEEE, 2017. [doi]
@inproceedings{LinWLL17,
title = {An ultra-low power 169-nA 32.768-kHz fractional-N PLL},
author = {Chun-Yu Lin and Tun-Ju Wang and Tzu-Hsuan Liu and Tsung-Hsien Lin},
year = {2017},
doi = {10.1109/ASSCC.2017.8240212},
url = {https://doi.org/10.1109/ASSCC.2017.8240212},
researchr = {https://researchr.org/publication/LinWLL17},
cites = {0},
citedby = {0},
pages = {45-48},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea (South), November 6-8, 2017},
publisher = {IEEE},
isbn = {978-1-5386-3178-2},
}