A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist

Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu. A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. In IEEE 25th International SOC Conference, SOCC 2012, Niagara Falls, NY, USA, September 12-14, 2012. pages 218-223, IEEE, 2012. [doi]

Abstract

Abstract is missing.