Wei Lin, Shao-Wei Yen, Yu-Cheng Hsu, Yu-Hsiang Lin, Li-Chun Liang, Tien-Ching Wang, Pei-Yu Shih, Kuo-Hsin Lai, Kuo-Yi Cheng, Chun-Yen Chang. A low power and ultra high reliability LDPC error correction engine with Digital Signal Processing for embedded NAND Flash Controller in 40nm COMS. In Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014. pages 1-2, IEEE, 2014. [doi]
@inproceedings{LinYHLLWSLCC14,
title = {A low power and ultra high reliability LDPC error correction engine with Digital Signal Processing for embedded NAND Flash Controller in 40nm COMS},
author = {Wei Lin and Shao-Wei Yen and Yu-Cheng Hsu and Yu-Hsiang Lin and Li-Chun Liang and Tien-Ching Wang and Pei-Yu Shih and Kuo-Hsin Lai and Kuo-Yi Cheng and Chun-Yen Chang},
year = {2014},
doi = {10.1109/VLSIC.2014.6858405},
url = {http://dx.doi.org/10.1109/VLSIC.2014.6858405},
researchr = {https://researchr.org/publication/LinYHLLWSLCC14},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014},
publisher = {IEEE},
isbn = {978-1-4799-3327-3},
}