A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages

Ming Ling, Qingde Lin, Ke Tan, Tianxiang Shao, Shan Shen, Jun Yang 0006. A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages. IEEE Trans. VLSI Syst., 29(12):2197-2209, 2021. [doi]

@article{LingLTSSY21,
  title = {A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages},
  author = {Ming Ling and Qingde Lin and Ke Tan and Tianxiang Shao and Shan Shen and Jun Yang 0006},
  year = {2021},
  doi = {10.1109/TVLSI.2021.3120653},
  url = {https://doi.org/10.1109/TVLSI.2021.3120653},
  researchr = {https://researchr.org/publication/LingLTSSY21},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {29},
  number = {12},
  pages = {2197-2209},
}