The following publications are possibly variants of this publication:
- RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanismXiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang. memsys 2019: 451-458 [doi]
- Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAMMing Ling, Xiaojing Shang, Shan Shen, Tianxiang Shao, Jun Yang. access, 7:111649-111661, 2019. [doi]
- TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply VoltagesShan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang 0006, Longxing Shi. tvlsi, 28(1):252-262, 2020. [doi]