Xiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang. RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism. In Proceedings of the International Symposium on Memory Systems, MEMSYS 2019, Washington, DC, USA, September 30 - October 03, 2019. pages 451-458, ACM, 2019. [doi]
Abstract is missing.