Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino. Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. In José L. Ayala, Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, Gilles Sicard, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings. Volume 6951 of Lecture Notes in Computer Science, pages 214-225, Springer, 2011. [doi]
@inproceedings{LingasubramanianCMMP11,
title = {Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating},
author = {Karthikeyan Lingasubramanian and Andrea Calimera and Alberto Macii and Enrico Macii and Massimo Poncino},
year = {2011},
doi = {10.1007/978-3-642-24154-3_22},
url = {http://dx.doi.org/10.1007/978-3-642-24154-3_22},
researchr = {https://researchr.org/publication/LingasubramanianCMMP11},
cites = {0},
citedby = {0},
pages = {214-225},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings},
editor = {José L. Ayala and Braulio García-Cámara and Manuel Prieto and Martino Ruggiero and Gilles Sicard},
volume = {6951},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-642-24153-6},
}