Abstract is missing.
- A Quick Method for Energy Optimized Gate Sizing of Digital CircuitsMustafa Aktan, Dursun Baran, Vojin G. Oklobdzija. 1-10 [doi]
- Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor ArchitecturesIgnacio Arnaldo, José L. Risco-Martín, José L. Ayala, José Ignacio Hidalgo. 11-21 [doi]
- A System Level Approach to Multi-core Thermal Sensors CalibrationAndrea Bartolini, MohammadSadegh Sadri, Francesco Beneventi, Matteo Cacciari, Andrea Tilli, Luca Benini. 22-31 [doi]
- Improving the Robustness of Self-timed SRAM to Variable VddsAbdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev, Alexandre V. Bystrov. 32-42 [doi]
- Architecture Extensions for Efficient Management of Scratch-Pad MemoryJosé V. Busquets-Mataix, Carlos Catalá, Antonio Martí Campoy. 43-52 [doi]
- Pass Transistor Operation Modeling for Nanoscale TechnologiesPanagiotis Chaourani, Ilias Pappas, Spiros Nikolaidis, Abdoul Rjoub. 53-62 [doi]
- Timing Modeling of Flipflops Considering Aging EffectsNing Chen, Bing Li, Ulf Schlichtmann. 63-72 [doi]
- Iterative Timing Analysis Considering Interdependency of Setup and Hold TimesNing Chen, Bing Li, Ulf Schlichtmann. 73-82 [doi]
- Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic TechnologyGregory di Pendina, Kholdoun Torki, Guillaume Prenat, Yoann Guillemenet, Lionel Torres. 83-91 [doi]
- Performance-Driven Clustering of Asynchronous CircuitsGeorgios D. Dimou, Peter A. Beerel, Andrew Lines. 92-101 [doi]
- Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal ProcessingAhmed Yasir Dogan, David Atienza, Andreas Burg, Igor Loi, Luca Benini. 102-111 [doi]
- Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-CoresThomas Ebi, Holm Rauchfuss, Andreas Herkersdorf, Jörg Henkel. 112-121 [doi]
- Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor NetworksNicolas Ferry, Sylvain Ducloyer, Nathalie Julien, Dominique Jutel. 122-132 [doi]
- Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAsIgnacio Herrera-Alzu, Marisa López-Vallejo. 133-142 [doi]
- Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS TechniqueHenry X. F. Huang, Steven R. S. Shen, James B. Kuo. 143-151 [doi]
- NBTI Mitigation by Giving Random Scan-in Vectors during Standby ModeToshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye. 152-161 [doi]
- An On-Chip All-Digital PV-Monitoring Architecture for Digital IPsHossein Karimiyan, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino. 162-172 [doi]
- Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value DistributionAlireza Khosropour, Hossein Aghababa, Ali Afzali-Kusha, Behjat Forouzandeh. 173-179 [doi]
- Using Silent Writes in Low-Power Traffic-Aware ECCMostafa Kishani, Amirali Baniasadi, Hossein Pedram. 180-192 [doi]
- SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor AgingChristoph Knoth, Carsten Uphoff, Sebastian Kiesel, Ulf Schlichtmann. 193-203 [doi]
- Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic MinimizationLingamneni Avinash, Christian C. Enz, Krishna V. Palem, Christian Piguet. 204-213 [doi]
- Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-GatingKarthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino. 214-225 [doi]
- A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard ConceptsOns Mbarek, Alain Pegatoquet, Michel Auguin. 226-236 [doi]
- Unified Gated Flip-Flops for Reducing the Clocking Power in Register CircuitsTakumi Okuhira, Tohru Ishihara. 237-246 [doi]
- C-elements for Hardened Self-timed CircuitsFlorent Ouchet, Katell Morin-Allory, Laurent Fesquet. 247-256 [doi]
- High-Speed and Low-Power PID Structures for Embedded ApplicationsAbdelkrim Kamel Oudjida, Nicolas Chaillet, Ahmed Liacha, Mustapha Hamerlain, Mohamed Lamine Berrandjia. 257-266 [doi]
- Design of Resonant Clock Distribution Networks for 3-D Integrated CircuitsSomayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli. 267-277 [doi]
- Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical ChannelsAmir-Mohammad Rahmani, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 278-287 [doi]
- Worst-Case Temperature Analysis for Different Resource Availabilities: A Case StudyLars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele. 288-297 [doi]
- A Framework for Architecture-Level Exploration of 3-D FPGA PlatformsHarry Sidiropoulos, Kostas Siozios, Dimitrios Soudris. 298-307 [doi]
- Variability-Speed-Consumption Trade-off in Near Threshold OperationMariem Slimani, Fernando Silveira, Philippe Matherat. 308-316 [doi]
- High Level Synthesis of Asynchronous Circuits from Data Flow GraphsRene van Leuken, Tom Van Leeuwen 0002, Huib Lincklaen Arriens. 317-330 [doi]
- A Secure D Flip-Flop against Side Channel AttacksBruno Vaquie, Sébastien Tiran, Philippe Maurine. 331-340 [doi]
- Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid CoolingFrancesco Zanini, David Atienza, Giovanni De Micheli. 341-350 [doi]