Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino. Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. In José L. Ayala, Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, Gilles Sicard, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings. Volume 6951 of Lecture Notes in Computer Science, pages 214-225, Springer, 2011. [doi]
Abstract is missing.