Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung. Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. on CAD of Integrated Circuits and Systems, 28(3):305-315, 2009. [doi]

Abstract

Abstract is missing.