A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs

Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin. A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. In 31st IEEE International System-on-Chip Conference, SOCC 2018, Arlington, VA, USA, September 4-7, 2018. pages 1-6, IEEE, 2018. [doi]

@inproceedings{LiuCWWL18,
  title = {A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs},
  author = {Chien-Tung Liu and Zhe-Wei Chang and Shih-Nung Wei and Jinn-Shyan Wang and Tay-Jyi Lin},
  year = {2018},
  doi = {10.1109/SOCC.2018.8618543},
  url = {https://doi.org/10.1109/SOCC.2018.8618543},
  researchr = {https://researchr.org/publication/LiuCWWL18},
  cites = {0},
  citedby = {0},
  pages = {1-6},
  booktitle = {31st IEEE International System-on-Chip Conference, SOCC 2018, Arlington, VA, USA, September 4-7, 2018},
  publisher = {IEEE},
  isbn = {978-1-5386-1491-4},
}