Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada. A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. In IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019. pages 256-258, IEEE, 2019. [doi]
@inproceedings{LiuSHDSPWWSSO19,
title = {A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS},
author = {Hanli Liu and Zheng Sun and Hongye Huang and Wei Deng and Teerachot Siriburanon and Jian Pang and Yun Wang and Rui Wu and Teruki Someya and Atsushi Shirane and Kenichi Okada},
year = {2019},
doi = {10.1109/ISSCC.2019.8662374},
url = {https://doi.org/10.1109/ISSCC.2019.8662374},
researchr = {https://researchr.org/publication/LiuSHDSPWWSSO19},
cites = {0},
citedby = {0},
pages = {256-258},
booktitle = {IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019},
publisher = {IEEE},
isbn = {978-1-5386-8531-0},
}