Cycle-count-accurate processor modeling for fast and accurate system-level simulation

Chen Kang Lo, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay. Cycle-count-accurate processor modeling for fast and accurate system-level simulation. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011. pages 341-346, IEEE, 2011. [doi]

Authors

Chen Kang Lo

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Li-Chun Chen

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Meng-Huan Wu

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Ren-Song Tsay

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