A Hardware Optimized High Throughput LDPC Decoder Supporting 3 Tb/s in 28 nm CMOS

Lukasz Lopacinski, Alireza Hasani, Goran Panic, Nebojsa Maletic, Jesús Gutiérrez 0004, Milos Krstic, Eckhard Grass, Rolf Kraemer. A Hardware Optimized High Throughput LDPC Decoder Supporting 3 Tb/s in 28 nm CMOS. In 2022 IEEE 33rd Annual International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), Kyoto, Japan, September 12-15, 2022. pages 1326-1331, IEEE, 2022. [doi]

Abstract

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