Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip Restle, Mary Yvonne Lanzerotti. Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. In John Lach, Gang Qu, Yehea I. Ismail, editors, Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005. pages 38-43, ACM, 2005. [doi]
Abstract is missing.