Mina Louis, Mohamed Dessouky, Ashraf Salem. PLL Real Number Modeling in SystemVerilog. In 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019, Lausanne, Switzerland, July 15-18, 2019. pages 257-260, IEEE, 2019. [doi]
@inproceedings{LouisDS19,
title = {PLL Real Number Modeling in SystemVerilog},
author = {Mina Louis and Mohamed Dessouky and Ashraf Salem},
year = {2019},
doi = {10.1109/SMACD.2019.8795233},
url = {https://doi.org/10.1109/SMACD.2019.8795233},
researchr = {https://researchr.org/publication/LouisDS19},
cites = {0},
citedby = {0},
pages = {257-260},
booktitle = {16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019, Lausanne, Switzerland, July 15-18, 2019},
publisher = {IEEE},
isbn = {978-1-7281-1201-5},
}