Ping Lu, Ying Wu, Pietro Andreani. A 90nm CMOS digital PLL based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter. In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012. pages 2593-2596, IEEE, 2012. [doi]
Abstract is missing.