Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee. A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 1955-1958, IEEE, 2007. [doi]
@inproceedings{LuWL07,
title = {A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter},
author = {Chi-Chang Lu and Jyun-Yi Wu and Tsung-Sum Lee},
year = {2007},
doi = {10.1109/ISCAS.2007.378359},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2007.378359},
researchr = {https://researchr.org/publication/LuWL07},
cites = {0},
citedby = {0},
pages = {1955-1958},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA},
publisher = {IEEE},
}