Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity - researchr publication authors

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Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang 0002. Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. In IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy. pages 1-5, IEEE, 2018. [doi]

This author has not been identified. Look up 'Guangyi Lu' in GoogleThis author has not been identified. Look up 'Yuan Wang' in GoogleThis author has not been identified. Look up 'Lizhong Zhang' in GoogleThis author has not been identified. Look up 'Yize Wang' in GoogleThis author has not been identified. Look up 'Ru Huang' in GoogleThis author has not been identified. Look up 'Xing Zhang 0002' in Google

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