Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity

Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang 0002. Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. In IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy. pages 1-5, IEEE, 2018. [doi]

@inproceedings{LuWZWH018,
  title = {Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity},
  author = {Guangyi Lu and Yuan Wang and Lizhong Zhang and Yize Wang and Ru Huang and Xing Zhang 0002},
  year = {2018},
  doi = {10.1109/ISCAS.2018.8350905},
  url = {https://doi.org/10.1109/ISCAS.2018.8350905},
  researchr = {https://researchr.org/publication/LuWZWH018},
  cites = {0},
  citedby = {0},
  pages = {1-5},
  booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy},
  publisher = {IEEE},
  isbn = {978-1-5386-4881-0},
}