Parameter optimization of Sallen-Key filters for removing DC voltage and high-order harmonics in PLL outputs while minimizing passband gain variation

Haibo Luo, Jianqiang Han, Ying Zhang, Weiwei Cao, Ge Shi 0001. Parameter optimization of Sallen-Key filters for removing DC voltage and high-order harmonics in PLL outputs while minimizing passband gain variation. Microelectronics Journal, 171:107121, 2026. [doi]

Authors

Haibo Luo

This author has not been identified. Look up 'Haibo Luo' in Google

Jianqiang Han

This author has not been identified. Look up 'Jianqiang Han' in Google

Ying Zhang

This author has not been identified. Look up 'Ying Zhang' in Google

Weiwei Cao

This author has not been identified. Look up 'Weiwei Cao' in Google

Ge Shi 0001

This author has not been identified. Look up 'Ge Shi 0001' in Google