The following publications are possibly variants of this publication:
- A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS ProcessZhicong Luo, Ming-Dou Ker. tbcas, 10(6):1087-1099, 2016. [doi]
- Design of Dual-Configuration Dual-Mode Stimulator in Low-Voltage CMOS Process for Neuro-ModulationChia-Chi Hsieh, Yi-Hui Wu, Ming-Dou Ker. tbcas, 17(2):273-285, April 2023. [doi]
- Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS ProcessChia-Chi Hsieh, Ming-Dou Ker. tbcas, 15(3):568-579, 2021. [doi]
- A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implantKuan-Yu Lin, Ming-Dou Ker, Chun-Yu Lin. iscas 2014: 237-240 [doi]
- A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical ApplicationsZhicong Luo, Ming-Dou Ker. esticas, 8(2):178-186, 2018. [doi]
- Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technologyMing-Dou Ker, Wei-Jen Chang. mr, 47(1):27-35, 2007. [doi]