Bjørnar Luteberget, Koen Claessen, Christian Johansen. Design-Time Railway Capacity Verification using SAT modulo Discrete Event Simulation. In Nikolaj Bjørner, Arie Gurfinkel, editors, 2018 Formal Methods in Computer Aided Design, FMCAD 2018, Austin, TX, USA, October 30 - November 2, 2018. pages 1-9, IEEE, 2018. [doi]
@inproceedings{LutebergetCJ18,
title = {Design-Time Railway Capacity Verification using SAT modulo Discrete Event Simulation},
author = {Bjørnar Luteberget and Koen Claessen and Christian Johansen},
year = {2018},
doi = {10.23919/FMCAD.2018.8603003},
url = {https://doi.org/10.23919/FMCAD.2018.8603003},
researchr = {https://researchr.org/publication/LutebergetCJ18},
cites = {0},
citedby = {0},
pages = {1-9},
booktitle = {2018 Formal Methods in Computer Aided Design, FMCAD 2018, Austin, TX, USA, October 30 - November 2, 2018},
editor = {Nikolaj Bjørner and Arie Gurfinkel},
publisher = {IEEE},
isbn = {978-0-9835678-8-2},
}