Abstract is missing.
- Functional Synthesis via Input-Output SeparationSupratik Chakraborty, Dror Fried, Lucas M. Tabajara, Moshe Y. Vardi. 1-9 [doi]
- k-FAIR = k-LIVENESS + FAIR Revisiting SAT-based Liveness AlgorithmsAlexander Ivrii, Ziv Nevo, Jason Baumgartner. 1-5 [doi]
- Trau: SMT solver for string constraintsParosh Aziz Abdulla, Mohamed Faouzi Atig, Yu-Fang Chen, Bui Phi Diep, Lukás Holík, Ahmed Rezine, Philipp Rümmer. 1-5 [doi]
- BMC with Memory Models as ModulesHernán Ponce de León, Florian Furbach, Keijo Heljanko, Roland Meyer. 1-9 [doi]
- Automata Learning for Symbolic ExecutionBernhard K. Aichernig, Roderick Bloem, Masoud Ebrahimi, Martin Tappler, Johannes Winter. 1-9 [doi]
- A Verified Certificate Checker for Finite-Precision Error Bounds in Coq and HOL4Heiko Becker, Nikita Zyuzin, Raphaël Monat, Eva Darulova, Magnus O. Myreen, Anthony C. J. Fox. 1-10 [doi]
- Expansion-Based QBF Solving Without RecursionRoderick Bloem, Nicolas Braud-Santoni, Vedad Hadzic, Uwe Egly, Florian Lonsing, Martina Seidl. 1-10 [doi]
- Post-Verification Debugging and Rectification of Finite Field Arithmetic Circuits using Computer Algebra TechniquesVikas Rao, Utkarsh Gupta, Irina Ilioaea, Arpitha Srinath, Priyank Kalla, Florian Enescu. 1-9 [doi]
- Complete Test Sets And Their ApproximationsEugene Goldberg. 1-9 [doi]
- Automatic Synchronization for GPU KernelsSourav Anand, Nadia Polikarpova. 1-9 [doi]
- Deductive Verification of Distributed Protocols in First-Order LogicOded Padon. 1 [doi]
- Complete and Efficient DRAT Proof CheckingAdrian Rebola-Pardo, Luís Cruz-Filipe. 1-9 [doi]
- Solving Constrained Horn Clauses Using Syntax and DataGrigory Fedyukovich, Sumanth Prabhu, Kumar Madhukar, Aarti Gupta. 1-9 [doi]
- Learning Linear Temporal PropertiesDaniel Neider, Ivan Gavran. 1-10 [doi]
- Design-Time Railway Capacity Verification using SAT modulo Discrete Event SimulationBjørnar Luteberget, Koen Claessen, Christian Johansen. 1-9 [doi]
- The FMCAD 2018 Graduate Student ForumDejan Jovanovic, Andrew Reynolds. 1 [doi]
- Analyzing the Fundamental Liveness Property of the Chord ProtocolJulien Brunel, David Chemouil, Jeanne Tawa. 1-9 [doi]
- Bit-Vector Interpolation and Quantifier Elimination by Lazy ReductionPeter Backeman, Philipp Rümmer, Aleksandar Zeljic. 1-10 [doi]
- Temporal Prophecy for Proving Temporal Properties of Infinite-State SystemsOded Padon, Jochen Hoenicke, Kenneth L. McMillan, Andreas Podelski, Mooly Sagiv, Sharon Shoham. 1-11 [doi]
- ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip VerificationHongce Zhang, Caroline Trippel, Yatin A. Manerkar, Aarti Gupta, Margaret Martonosi, Sharad Malik. 1-10 [doi]
- Using Loop Bound Analysis For Invariant GenerationPavel Cadek, Clemens Danninger, Moritz Sinn, Florian Zuleger. 1-9 [doi]
- Semantic-based Automated Reasoning for AWS Access Policies using SMTJohn Backes, Pauline Bolignano, Byron Cook, Catherine Dodge, Andrew Gacek, Kasper Luckow, Neha Rungta, Oksana Tkachuk, Carsten Varming. 1-9 [doi]
- Certifying Proofs for LTL Model CheckingAlberto Griggio, Marco Roveri, Stefano Tonetta. 1-9 [doi]
- Rely-Guarantee Reasoning for Automated Bound Analysis of Lock-Free AlgorithmsThomas Pani, Georg Weissenbacher, Florian Zuleger. 1-9 [doi]
- Template-Based Verification of Heap-Manipulating ProgramsViktor Malík, Martin Hruska, Peter Schrammel, Tomás Vojnar. 1-9 [doi]
- The ELDARICA Horn SolverHossein Hojjat, Philipp Rümmer. 1-7 [doi]
- Formal Verification of Deep Neural NetworksNina Narodytska. 1 [doi]
- CoSA: Integrated Verification for Agile Hardware DesignCristian Mattarei, Makai Mann, Clark Barrett, Ross G. Daly, Dillon Huff, Pat Hanrahan. 1-5 [doi]
- Analysis of Relay Interlocking Systems via SMT-based Model Checking of Switched Multi-Domain Kirchhoff NetworksRoberto Cavada, Alessandro Cimatti, Sergio Mover, Mirko Sessa, Giuseppe Cadavero, Giuseppe Scaglione. 1-9 [doi]